This is a follow-up to the article Verification Needed to Take High-Level Synthesis Mainstream by Tom Anderson that appeared on EDACafé. The post is well-written and in an intelligent manner that makes you want to check out what Breker Verification Systems (the company whose Tom is VP of Marketing) does. I'm saying this because this is in sharp contrast to the
ads articles that appear on SemiWiki and are posted on LinkedIn as spam discussions.
Anyway, in this post I explain why I don't think that HLS can be successful, and why this has to do with the so-called "paradigm shift" (see the title of this post).
All that's missing?
Tom claims that "what is keeping [HLS] from being a mainstream technology used for every chip design" is verification. You know what I feel this sounds like? "Just add this feature to your product and I'll buy it for sure". You can keep adding features, a prospect will always find reasons not to use your product if they don't want to. If all HLS needed was sequential equivalence checking, we'd all be using Calypto and RTL would be long gone. Clearly something else is at play here!
Maybe the input languages are not appropriate? Many HLS tools start from what they call C++ -- which are often just ugly proprietary C-like subsets of C++ more than real C++. And it's impossible to design an IP core (let alone a full chip) in C++, except for basic DSP algorithms, because anything requiring finely tuned parallelism is doomed to fail; sequential, software languages are just not designed for this.
SystemC is a better attempt at adding parallelism to C/C++, but guess what? Like VHDL, like Verilog, and like so many other languages, SystemC is mainly a simulation framework. This should mean that at least it would be good at, well, simulating, which again should be perfect for verification. The fact that it is not is perhaps a sign that something is wrong.
The paradigm shi(f)t is just too big!
What if the problem is simply that the untimed sequential paradigm is too different from the transistors? If we look at software, it is often trivial to build a mental representation of a program in any imperative sequential language as a sequence of instructions, which is not too far from a Turing machine. Functional languages are something else, instead of executing statements you evaluate expressions, but you still figure out how your program will be executed.
This is exactly what is not possible with High-Level Synthesis. As a human, you have no idea how the final hardware architecture will look like. How would you expect a tool to prove an equivalency?