As part of my series on designing a Bitcoin IP, I am collecting different synthesis results on the two leading FPGA providers (Altera and Xilinx) as well as the challenger Lattice Semiconductors. For those who wonder why Lattice, it so happens that we bought the Versa Development Kit a while back when it was sold at the exceptional price of $99 (which was a very good bargain for PCI Express, two 1Gbps Ethernet ports and 1Gb DDR3 RAM). With that cleared up, we can start the review. Keep in mind that my background is software, so you may have an entirely different experience with synthesis tools than I had.
Lattice's development environment, Diamond, does a pretty good job overall. The version 2.2 of Diamond is available in 32-bit and 64-bit for Linux and Windows, and is only a 1.3 GB download, which makes it the smallest of the three tools, and it is 4 times smaller than Xilinx ISE! I find that the tool has a well-thought layout, with a "File list" tab and a "Process" tab. But its best feature is the inclusion of Synopsys' Synplify Pro: having a dedicated synthesis tool makes a difference, it also has very good RTL and technology viewers which are invaluable when you want to look at the hardware that is synthesized (see the image below). Synplify provides you with good, easy-to-read reports, it estimates the maximum frequency and shows you the critical path in the RTL view.
Altera's development environment Quartus II feels more sophisticated than Diamond, which is really a double-edged sword, as I find it a bit messy for newcomers. Regardless, you can now download the tool as individual files, so you only download what you need (tools and devices). This can make a huge difference if you don't need the "Modelsim-Altera Edition" and only use one or two devices! Like Diamond it is available in 32-bit and 64-bit for Linux and Windows. Note that even with individual files, you can quickly end up with a 3GB download (1.7GB Quartus, 350MB help, 750MB one device, 140MB device programmer).
As I mentioned, the tool has a more sophisticated feeling than Diamond, but it is also less easy to get started with it. The synthesizer gives detailed warnings; the RTL view is more colorful than Synplify (registers are blue, muxes are parallelograms), but less concise. Below is Synplify's RTL view compared to Quartus' RTL view:
Something that is a bit annoying with Quartus is that to get an "Early Timing Estimate", you have to go through the Fitter (Place&Route), which takes a bit of time compared to Synplify's timing estimation which is done during synthesis. You can locate the worst-case timing paths in the RTL viewer, although you have to remember that it is a right-click and "Locate in RTL Viewer" (the last, and last but one entry in their respective menus...). Remember when I said it was less easy to get started with? :-)
As Xilinx is the leading FPGA provider, I wanted to synthesize my SHA-256 IP on Xilinx to compare the results with commercial implementations. I head to Xilinx, download the Vivado tool suite, which is their new development environment. The tagline of Vivado is "Productivity. Multiplied", something which could not be farther from the truth.
Like Diamond and Quartus, Vivado is supposed to work on Windows 32-bit and 64-bit. Except that, contrary to them, it does not support Windows 8 (even though Windows 8 is mostly backward compatible). It just fails with this beautiful message:
start_gui ERROR: [Common 17-612] start_gui is not supported on Windows8.
You have to start the batch file by yourself to see this, because by default it does not even print anything! Yes because unlike the other tools, you start Vivado with a .bat file :shock: This reminds me of the not so good old days of MS-DOS :D You can trick 'vivado.exe' into believing it is running on Windows 7 (thanks to the 'Compatibility' tab), but then Vivado makes the Java VM crash. It turns out that according to a Xilinx employee (administrator of their forum, see here):
Windows 8 is not planned to be supported until at least 2014. The roadmap for full support will be driven by customer adoption.
Ok. I don't see why not, since no other software I know has any trouble with Windows 8, but hey it's Xilinx. Vivado HLS, though, does work on Windows 8 :-? Could it be a way to artificially have more people try Vivado HLS? I don't know. Anyway, I went for the (what I thought would be a) failsafe solution: back to ISE.
The ugly's cousin
ISE is the fat ugly cousin of Vivado, you get to download a 6 GB tar archive, that when you finish downloading you have to un-tar. Wouldn't it be the job of the installer? I suspect that the problem is that 32-bit systems would have trouble if they had to deal with a 6 GB executable. There could be a 64-bit executable without that problem, or they could do it the Altera way, but no. Anyway, the installation of ISE completes and it launches the license manager, which just hangs (but does not crash). No explanation, so I circumvent the problem by modifying the XILINXDLICENSEFILE. Let me skip the part about getting an evaluation license from the Xilinx website, which is confusing at best, and here I am, finally starting to use a development environment that works on my Windows 8 system. Or so I thought...
As you see below, trying to open a project just makes ISE crash:
Actually, trying to do almost anything such as adding a file to a project, changing the strategy, etc. results in a crash. Why? Well, you see, my system is not only Windows 8, it is also 64-bit. Something that I expect to be quite common nowadays among professionals (the 64-bit instruction set for x86 has been around for more than 10 years after all). Not for Xilinx apparently... This thread on the Xilinx forums is particularly fun to read :D
I end up running ISE in 32-bit mode, which works! I don't know what Vivado's RTL view looks like, but I certainly hope it's better than ISE's:
This concludes this post on the development environments provided by three FPGA vendors Altera, Lattice, and Xilinx. I hope you liked it, and please share your experience with these or other FPGA tools in the comments. Thanks!